The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through an underlying channel between the source and drain regions.
Power MOS devices, including lateral diffused MOS (LDMOS) devices, are employed in a wide variety of applications, such as, for example, power amplifiers in wireless communications systems. LDMOS devices are generally characterized by the use of an epitaxial silicon layer on a more highly doped silicon substrate. While useful in many applications, LDMOS devices are not without drawbacks. For example, “hot carrier injection” (HCI) degradation can significantly limit the performance of these devices. As is well known in the art, the HCI phenomenon generally results from heating and subsequent injection of charge carriers into the gate oxide and/or an oxide layer above a drift region of an LDMOS device. This injection of charge carriers often results in a localized and non-uniform buildup of interface states and oxide charges near and underneath a gate and/or in the drift region of the device. For example, HCI can produce variations in certain characteristics of the LDMOS device, including saturation current, threshold voltage, transconductance, on-resistance, etc., thus undesirably affecting the performance and reliability of the device. The amount of HCI degradation in the device can be measured as a function of the amount of increase in the on-resistance of the device (on-resistance degradation) and/or the amount of decrease in the saturation current (saturation current degradation) in the device.
A conventional LDMOS device typically includes a lightly-doped drain (LDD) region which is often formed at or near an upper surface interface between the epitaxial silicon layer and the gate oxide of the device. Locating the LDD region in close relative proximity to the silicon/oxide interface, however, significantly increases the likelihood that charged carriers will become trapped at the interface, thereby increasing HCI degradation in the device.
In many applications, such as, for example, power amplifier applications, it is desirable to minimize the on-resistance associated with the device. In an LDMOS device, the on-resistance is dominated primarily by the characteristics of the LDD region, thus a known methodology for reducing the on-resistance increases a doping concentration of the LDD region. However, since the LDD region is typically formed at the silicon/oxide interface of the device, as previously stated, increasing the doping concentration of the LDD region also undesirably increases HCI degradation in the device. The increase in HCI degradation resulting from the increased doping concentration of the LDD region often significantly undermines any beneficial reduction in on-resistance that may otherwise be achieved by increasing the doping concentration of the LDD region. Furthermore, by increasing the doping concentration of the LDD region in the device, the breakdown voltage of the device is undesirably reduced.
Accordingly, it is desirable to provide improved LDMOS devices capable of controlling HCI degradation that do not suffer from one or more of the problems exhibited by conventional LDMOS devices. Moreover, it is desirable to provide such improved LDMOS devices that are compatible with existing integrated circuit (IC) fabrication process technologies. In addition, it is desirable to provide methods for fabricating such LDMOS devices. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.